/*
 * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */


#ifndef HPM_BATT_IOMUX_H
#define HPM_BATT_IOMUX_H

/* IOC_PZ00_FUNC_CTL function mux definitions */
#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ00_FUNC_CTL_BATT_PWR_ON          IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1)
#define IOC_PZ00_FUNC_CTL_BATT_TAMPER_00       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)

/* IOC_PZ01_FUNC_CTL function mux definitions */
#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ01_FUNC_CTL_BATT_RESETN          IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1)
#define IOC_PZ01_FUNC_CTL_BATT_TAMPER_01       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)

/* IOC_PZ02_FUNC_CTL function mux definitions */
#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ02_FUNC_CTL_BATT_PBUTN           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1)
#define IOC_PZ02_FUNC_CTL_BATT_TAMPER_02       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)

/* IOC_PZ03_FUNC_CTL function mux definitions */
#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ03_FUNC_CTL_BATT_WBUTN           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1)
#define IOC_PZ03_FUNC_CTL_BATT_TAMPER_03       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)

/* IOC_PZ04_FUNC_CTL function mux definitions */
#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ04_FUNC_CTL_BATT_PLED            IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1)
#define IOC_PZ04_FUNC_CTL_BATT_TAMPER_04       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)

/* IOC_PZ05_FUNC_CTL function mux definitions */
#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ05_FUNC_CTL_BATT_WLED            IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1)
#define IOC_PZ05_FUNC_CTL_BATT_TAMPER_05       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)

/* IOC_PZ06_FUNC_CTL function mux definitions */
#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ06_FUNC_CTL_BATT_TAMPER_06       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)

/* IOC_PZ07_FUNC_CTL function mux definitions */
#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07           IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0)
#define IOC_PZ07_FUNC_CTL_BATT_TAMPER_07       IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2)
#define IOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07        IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3)


#endif /* HPM_BATT_IOMUX_H */
